A field effect transistor comprises doped source and drain regions. These doped source and drain regions conventionally are formed on a substrate of a semiconductor material. A parasitic source/drain junction capacitance develops in such devices due to the junctions of the source and drain with the substrate. Junction capacitances may be undesirable because, since they must be charged before current can flow, they may slow down the field effect transistor.
In order to reduce the junction capacitance in field effect transistors occurring due to the junctions of the source and drain with the substrate, previous efforts have attempted to place an oxide region between the source and substrate and another oxide region between the drain and substrate. In one of these efforts a field effect transistor is fabricated with a minimum length between oxide regions that is approximately the same as the gate length. The use of such a technique results in a non-planar gate oxide due to the inclusion of the additional oxide regions. Non-planar gate oxide may be disadvantageous. For example, devices formed with non-planar gate oxide may suffer gate oxide integrity problems.
In another approach, a field effect transistor is fabricated with a source and drain on oxide regions with a minimum distance between oxide regions greater or significantly greater than the length of the gate. In such a technique, the oxide regions may not completely isolate the source and drain regions from the substrate. Therefore, the junction capacitance associated with these devices is only marginally better than bulk CMOS devices. Additionally, the oxide regions do not restrict the source and drain depths. Thus, short channel effects are similar to those associated with bulk CMOS devices.